1. Field of the Invention
The present invention relates to a semiconductor chip on which an electrical circuit is arranged including circuit devices such as transistors and resistors connected with each other by wiring. More particularly, the present invention relates to a semiconductor chip and an inspection method suitable for efficient identification of defects produced when the chip is formed from a wafer.
2. Description of the Prior Art
FIG. 11 is a front view showing the configuration of a prior art semiconductor chip. In the Figure, reference numerals 6 each designate internal circuits formed on a central part of a semiconductor substrate; reference numerals 5 each designate external connection pads which are arranged along a peripheral edge of the semiconductor substrate for connection of bonding wires and so on thereto; and reference numerals 19 each designate external inputting/outputting lines for respectively connecting each of the external connection pads 5 with each of the internal circuits 6.
Besides, such a semiconductor chip is formed by forming circuit devices such as transistors, using techniques such as an ion implantation, on a wafer composed of a semiconductor and, after laminating wirings for connecting the circuit devices with each other on the wafer, by dicing of the wafer.
Since the prior art semiconductor chip is configured as stated above, chipping occurs at the time of the dicing, diffusion variations occur in diffusion region by a change in factors such as ion implantation efficiency, or there arise variations in thickness of the wirings. In particular, concerning the above-mentioned wafer, a single crystal rod, which is an original material thereof, is formed in a cylindrical shape, and also, in recent years, an area of the wafer tends to be upsized. Consequently, there is a tendency to easily produce characteristic differences between a central part and a peripheral part of the wafer, and it becomes impossible to avoid the occurrences of such problems described above.
In addition, in the prior art, in order to distinguish and select this kind of defective chips as early as possible, an interface test (hereinafter, referred to as "IF test") is carried out at the beginning of a chip test. The IF test is, in general, a test to bring a single probe needle into contact with every external connection pad 5, measure a diode characteristic using this probe needle, and perform acceptable/defective product judgement by comparing the measurement result with a predetermined characteristic. If a chip is an acceptable chip as is the case with the above-mentioned FIG. 11, the chip passes the chip test and is then sent to a next semiconductor device fabricating process.
Incidentally, performed as the chip test other than this are tests such as an electrical characteristic test and a function test.
As above, the IF test is the test to bring an inspection needle into contact with every external connection pad 5, measure the diode characteristic of the semiconductor substrate being in the state, and perform the acceptable/defective product judgement depending on whether the result is the desired one or not.
FIG. 12 is a front view showing a configuration of a prior art semiconductor chip about 30% of the area of which has been chipped. In the Figure, reference numerals 21 each designate chipped external connection pads which are supposed to be disposed inside the above-mentioned chipped region, and reference numerals 20 each designate chipped external inputting/outputting lines which are supposed to be disposed inside the above-mentioned chipped region. The construction other than the above described is similar to that in FIG. 11, and thus the same numerals designate like elements and the description of them will be omitted. In case of such a prior art semiconductor chip about 30% of which has been chipped, it is possible to reject the chip as a defective product at the above-described IF test because the chip lacks the external connection pads 21.
On the other hand, FIG. 13 is a front view showing a configuration of a prior art semiconductor chip about 10% of the area of which has been chipped. The construction other than the above described is similar to that in FIG. 12, and thus the same numerals designate like elements and the description of them will be omitted. In case of such a semiconductor chip about 10% of which has been chipped, the chip must usually be rejected as a defective product in order to assure the reliability at the time of being formed into a semiconductor device. In this case, however, there exist all the external connection pads 5. Consequently, it turns out that the desired characteristic is obtained at the above-mentioned IF test and thus it becomes impossible to reject the chip as a defective product.
As a result, in order to distinguish and select this kind of defective product in an actual manufacturing process, each semiconductor chip had to be inspected by employing a visual inspection thereof. In such an inspection in reliance on help of humans, there occur variations in the content inspected. Consequently, there remain chips which, essentially, have to be judged as defective products so as to maintain the above-described reliability, and eventually there remains a possibility that a semiconductor device in which such defective chips are used has been formed.
Also, with the above-mentioned IF test, depending on the relation between the chipped members/region and an inspecting order of the external connection pads 5, there is a case in which it is not until a plurality of external connection pads 5 are inspected that the chip has been judged as a defective product. In that case, there exists a problem that the inspecting time, which was needed for measuring the external connection pads 5 until then, has ended in vain.
Accordingly, as disclosed in JP-A No. Hei 2-312255, it can be considered to judge a chipped or damaged chip at a testing process specifically designed therefor. FIG. 14 is a front view showing a configuration embodiment of another prior art semiconductor chip to which such an inspecting method is applied. In the Figure, reference numerals 22 each designate detecting pads provided independently of the external connection pads 5, and reference numeral 23 designates a detecting line disposed along the whole peripheral edge of the chip and connecting the two detecting pads 22, 22 with each other. The construction other than the above described is similar to that in the prior art semiconductor chip shown in FIG. 11, and thus the same numerals designate like elements and the description of them will be omitted.
Also, FIG. 15 is a front view showing a configuration of the another prior art semiconductor chip about 10% of the area of which has been chipped, and FIG. 16 is a front view showing a configuration of the another prior art semiconductor chip about 30% of the area of which has been chipped.
Incidentally, in the Figures, reference numeral 26 designates a chipped inspecting line which is supposed to be disposed inside the chipped region, and reference numerals 25 designate chipped external inputting/outputting pads which are supposed to be disposed inside the chipped region.
Moreover, in such a method of inspecting a semiconductor chip, a probe needle is brought into contact with the above-stated two detecting pads 22, 22. If an electrical conduction is found therebetween, the chip is judged to be an acceptable product, and if no electrical conduction is found, the chip is judged to be a defective product. Thus, it is possible to judge, as a defective product, not only the semiconductor chip on which the external connection pads 25 are chipped as shown in FIG. 16 but also the semiconductor chip chipped to such an extent that the external connection pads 5 are not chipped as shown in FIG. 15, because the chipping can be detected as a chipping of the inspecting line 26. As a result, it becomes possible to assure the reliability of a semiconductor device, and what is more, to perform the inspecting with a high efficiency.
However, if trying to form the detecting pads 22, and inspecting line 26 specifically designed for simply detecting the chipping only in this way, there emerges a problem of an increase in the chip area.